1. Field of the Invention
The invention relates to a method of fabricating a flash memory. and more particularly to a method of fabricating a flash memory with a self-aligned source.
2. Description of the Related Art
Non-volatile memories are applied to a variety of electronic devices for the functions of storing structure data, programming data, or data which can be accessed iteratively. In the application of non-volatile memories, the electrically erasable and programmable characteristics of the electrically erasable read only memory (EEPROM), especially the flash memory, are further emphatic. For EEPROMs, a more flexible application in transforming data is obtained by a flash memory during the fabricating process, or in an electronic device product. In the U.S. Pat. No. 5,416,349, a typical example of a flash memory is disclosed by Bergemont. The flash memory comprises a sharing source and buried bit line. The structure of sharing a source and a bit line has a high density, and therefore, reduce the cost of production. The field of flash memory is very wide that it is verv sensitive for the cost. Thus, for fabricating a flash memory, the cost is a key factor.
In a flash EEPROM, the floating gate on the floating gate transistor is used to selectively store charges. FIG. 1 shows a simple stacked structure of a non-volatile memory device. An isolation region 11 is formed on a substrate 10, to define an active region. A spacer is formed on the substrate 10 for the isolation between adjacent devices. A gate oxide layer 12 of a floating gate transistor is formed on the substrate 10. A gate electrode structure is fonned on the gate oxide layer 12. The gate electrode structure comprises a poly-silicon floating gate 13, an inter-dielectric layer 14, and a doped poly-silicon controlling gate 15. A spacer is formed on the side wall of the gate electrode structure. On the substrate 10, a channel region is defined between the source/drain region 17. The source/drain region 17 is located between the gate electrode structure and the isolation region 11.
FIG. 2 shows the structure of a conventional array of a flash memory. On a semiconductor substrate (not shown), a gate oxide layer (not shown) is formed. Parallel poly-silicon lines isolated by an oxide layer 20 are formed on the gate oxide layer. A dielectric layer (not shown) is formed on the poly-silicon lines. Word lines 21 are then formed and defined perpendicular to the poly-silicon lines with a predetermined distance with each other. While defining the word lines 21, the poly-silicon lines are defined to form tloating gates 22 simultaneously. Meanwhile, drain regions 23 and source regions 24 are also defined.
The layout of a conventional array of a flash memory array is also shown on FIG. 2. Due to the shift of plhoto-masks, a misalignment is very likely to happen, and hence the dimension of each source line is different from each other. The source erase characteristics of each source line are, therefore, different from each other. Thus, in the conventional flash memory array, an alignment margin .alpha. is formed between the word lines 21 and the source regions 24.